Monolithic multi-i region diode switches

ABSTRACT

Monolithic multi-throw diode switch structures are described. The monolithic multi-throw diode switches include a hybrid arrangement of diodes with different intrinsic regions. In one example, a method of manufacture of a monolithic multi-throw diode switch includes providing an intrinsic layer on an N-type semiconductor substrate, implanting a first P-type region to a first depth into the intrinsic layer to form a first PIN diode comprising a first effective intrinsic region of a first thickness, implanting a second P-type region to a second depth into the intrinsic layer to form a second PIN diode comprising a second effective intrinsic region of a second thickness, and forming at least one metal layer over the intrinsic layer to electrically couple the first PIN diode to a node between a common port and a first port of the switch.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No.16/805,154, filed Feb. 28, 2020, titled “MONOLITHIC MULTI-I REGION DIODESWITCHES,” which claims the benefit of priority to U.S. ProvisionalApplication No. 62/811,734, filed Feb. 28, 2019, titled “MONOLITHICMULTI-THROW MULTI-I REGION PIN DIODE SWITCHES,” the entire contents ofboth of which are hereby incorporated herein by reference.

BACKGROUND

A PIN (P-type-Intrinsic-N-type) diode is a diode with an undopedintrinsic semiconductor region between a P-type semiconductor region andan N-type semiconductor region. Traditionally, PIN diode devices havebeen fabricated by the growth, deposition, or other placement of layersvertically on a substrate. A PIN diode is a diode with an undopedintrinsic semiconductor region between a P-type semiconductor region andan N-type semiconductor region. The P-type and N-type regions aretypically heavily doped because they are used for ohmic contacts. Theinclusion of the intrinsic region between the P-type and N-type regionsis in contrast to an ordinary PN diode, which does not include anintrinsic region.

The top, P-type region is the anode of the PIN diode, and the bottom,N-type region or substrate is the cathode of the PIN diode. Whenunbiased, the PIN diode is in a high impedance state and can berepresented as a capacitor, the capacitance of which is given byC=A_(Anode)D_(si)E_(o)/T, where: A_(Anode) is the area of the anode,D_(si) is the dielelectric constant of the intrinsic silicon, E_(o) isthe permittivity of free space, and T is the distance between the anodeand cathode.

If a positive voltage larger than a threshold value is applied to theanode with respect to the cathode, a current will flow through the PINdiode and the impedance will decrease. A PIN diode in a forward biasedstate can be represented as a resistor whose value decreases to aminimum value as the current through the PIN diode increases. The biasto change the PIN diode from the high impedance (off) state to the lowimpedance (on) state can be DC or AC. In the case of an AC voltage, themagnitude must be greater than the threshold value and the duration ofthe positive voltage must be longer than the transit time of carriersacross the intrinsic region.

SUMMARY

A number of monolithic diode switches for applications in radiofrequency circuits are described. In one example, a monolithicmulti-throw diode switch includes a common port, a first port, and asecond port. The switch also includes a first PIN diode comprising afirst P-type region formed to a first depth into an intrinsic layer suchthe first PIN diode comprises a first effective intrinsic region of afirst thickness, where the first PIN diode is electrically coupled to anode between the common port and the first port. The switch alsoincludes a second PIN diode comprising a second P-type region formed toa second depth into the intrinsic layer such the second PIN diodecomprises a second effective intrinsic region of a second thickness,where the second PIN diode is electrically coupled to a node between thecommon port and the second port. The switch also includes a first biasnetwork for bias control of the first PIN diode, and a second biasnetwork for bias control of the second PIN diode.

In one aspect of the embodiments, the first thickness of the first PINdiode is greater than the second thickness of the second PIN diode. Thisconfiguration allows for both the thinner intrinsic region PIN diode andthe thicker intrinsic region PIN diode to be individually optimized. Asone example, for a switch functioning in a dedicated transmit/receivemode, the first transmit PIN diode can have a thicker intrinsic regionthan the second receive PIN diode to maximize power handling for thetransmit arm and maximize receive sensitivity and insertion loss in thereceive arm.

In another aspect of the embodiments, the switch can also include atleast one capacitor and at least one inductor formed over the intrinsiclayer as part of the monolithic multi-throw diode switch. In otherexamples, the switch can also include at least one transmission lineformed over the intrinsic layer as part of the monolithic multi-throwdiode switch. These additional circuit elements, along with metal layersto interconnect all elements of the switch, can be realizedmonolithically to improve the overall reliability, circuit ruggedness,radio frequency (RF) performance, circuit size, and overall cost of theswitch as compared to discrete solutions.

As examples of the monolithic diode switch topologies described herein,the first PIN diode can be series-connected in the node between thecommon port and the first port, and the second PIN diode can beseries-connected in the node between the common port and the secondport. In another case, the first PIN diode can be shunt-connected fromthe node between the common port and the first port to ground, and thesecond PIN diode can be shunt-connected from the node between the commonport and the second port to ground. In still another case, the first PINdiode can be series-connected in the node between the common port andthe first port, and the second PIN diode can be shunt-connected from acathode of the first PIN diode to ground. Other topologies are describedherein.

In other aspects of the embodiments, the monolithic diode switch canalso include a dielectric layer over the intrinsic layer, where thedielectric layer includes a plurality of openings, the first P-typeregion is formed through a first opening among the plurality ofopenings, and the second P-type region is formed through a secondopening among the plurality of openings. The first width of the firstopening can be different than a second width of the second opening.

In another embodiment, a method of manufacture of a monolithicmulti-throw diode switch is described. The method includes providing anintrinsic layer on an N-type semiconductor substrate, implanting a firstP-type region to a first depth into the intrinsic layer to form a firstPIN diode comprising a first effective intrinsic region of a firstthickness, implanting a second P-type region to a second depth into theintrinsic layer to form a second PIN diode comprising a second effectiveintrinsic region of a second thickness, and forming at least one metallayer over the intrinsic layer to electrically couple the first PINdiode to a node between a common port and a first port of the switch andto electrically couple the second PIN diode to a node between the commonport and a second port of the switch. In one aspect of the embodiment,the first thickness is greater than the second thickness. The method canalso include forming at least one capacitor and at least one inductorover the intrinsic layer as part of the monolithic multi-throw diodeswitch.

The method can also include forming an insulating layer on the intrinsiclayer, and forming a first opening in an insulating layer. In that case,implanting the first P-type region can include implanting the firstP-type region through the first opening. After implanting the firstP-type region, the method can also include forming a second opening inthe insulating layer. In that case, implanting the second P-type regioncan include implanting the second P-type region through the secondopening. In this example, a first width of the first opening isdifferent than a second width of the second opening.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure can be better understood withreference to the following drawings. It is noted that the elements inthe drawings are not necessarily to scale, with emphasis instead beingplaced upon clearly illustrating the principles of the embodiments. Inthe drawings, like reference numerals designate like or corresponding,but not necessarily the same, elements throughout the several views.

FIG. 1A illustrates an example vertical planar silicon PIN diodestructure with multi-thickness intrinsic regions according to variousembodiments described herein.

FIG. 1B illustrates an example method of forming the PIN diode structureshown in FIG. 1A according to various embodiments described herein.

FIG. 2 illustrates an example HMIC silicon PIN diode structure accordingto various embodiments described herein.

FIG. 3 illustrates another example HMIC silicon PIN diode structureaccording to various embodiments described herein.

FIG. 4A illustrates another example HMIC silicon PIN diode structurewith multi-thickness intrinsic regions according to various embodimentsdescribed herein.

FIG. 4B illustrates another example HMIC silicon PIN diode structurewith multi-thickness intrinsic regions according to various embodimentsdescribed herein.

FIG. 5 illustrates another example HMIC silicon PIN diode structure withmulti-thickness intrinsic regions according to various embodimentsdescribed herein.

FIG. 6 illustrates an example series-connected single pole doublethrough (SPDT) switch according to various embodiments described herein.

FIG. 7 illustrates an example shunt-connected SPDT switch according tovarious embodiments described herein.

FIG. 8 illustrates an example series-shunt-connected SPDT switchaccording to various embodiments described herein.

FIG. 9 illustrates an example series-connected TEE SP3T switch accordingto various embodiments described herein.

FIG. 10 illustrates an example series-shunt-connected ring switchaccording to various embodiments described herein.

DETAILED DESCRIPTION

Discrete PIN diodes are available in various forms, such as in bare ordiscrete die form, in plastic packages, and in ceramic packages ofvarious types (e.g., surface mount, pill packages, etc.). PIN diodes inceramic packages are particularly suitable for waveguide, coaxial, andsurface mount applications, while PIN diodes in bare die form are oftenused for chip and wire high frequency microwave applications.

However, many of the current design and fabrication techniques for PINdiodes are limited. These techniques cannot be used to form differentPIN diode structures, such as PIN diodes with different intrinsic regionthicknesses, on a single silicon wafer. Thus, the current design ofmulti-throw RF switches generally requires the use of a number ofdiscrete PIN diodes, each formed from a different silicon wafer, toincorporate PIN diodes with different intrinsic region thicknesses intoone multi-throw switch. These switches are formed by using a hybridassembly of individual discrete PIN diodes mounted on a PCB or anothermulti-chip module format. The number of stages and specific arrangementof PIN diodes in each stage determines the low level RF turn-on, theflat leakage, and the power handling/limiting and frequency response. Amonolithic (i.e., integrated silicon) solution would improve the overallreliability, circuit ruggedness, RF performance, circuit size, andoverall cost of multi-throw switches and other circuits as compared todiscrete solutions.

As noted above, the current design and fabrication techniques for planarPIN diodes limit the types of diode structures that can be realizedacross a silicon wafer. For example, one fabrication technique for PINdiodes limits all the PIN diodes fabricated on a silicon wafer to eachhave the same “I” (i.e., intrinsic) region thickness. This is a resultof several factors. First, PIN diodes are almost exclusively verticalstructures, where a metallurgical “I” region is grown or wafer bondedover a highly doped N-type substrate, where the N-type substrate formsthe N+ cathode. The P+ anode is then formed in the “I” region either byion implantation or solid state deposition of a P-type dopant, followedby a heat cycle to activate and diffuse the P-type dopant to a speciedepth into the “I” region. The junction depth of the P+ anode after thethermal drive cycle will result in a reduction of the metallurgical “I”region thickness resulting in an effective or electrical “I” regionthickness. This approach results in a wafer and subsequent derivativedie having an “I” region of only one thickness. In other words, everyPIN diode formed through this approach has the same “I” regionthickness. For many high frequency circuit functions, however, it isnecessary to have PIN diodes with multiple “I” region thicknesses, toachieve a control response over a desired frequency range, for example,and for other operating characteristics.

Another example fabrication technique for PIN diodes is described inU.S. Pat. No. 7,868,428. U.S. Pat. No. 7,868,428 describes the formationof multiple thickness “I” regions on a single wafer using aphotolithographic process and lateral gaps between separate P+ and N+regions. The P+ and N+ regions are ion implanted/diffused into anundoped intrinsic silicon wafer or intrinsic region of a wafer. Thedifficulty with this lateral surface controlled approach is the factthat relatively high surface leakage, which is in general at least 10times the leakage levels observed for bulk, vertical devices, produces avery inconsistent turn-on characteristic.

Due in part to the limitations outlined above, the current design ofmulti-throw switches generally requires the use of a number of discretePIN diodes, each formed from a different silicon wafer, to incorporatePIN diodes with different “I” region thicknesses into one multi-throwswitch. These switches use a hybrid assembly of individual discrete PINdiodes mounted on a printed circuit board (PCB), for example, or anothermulti-chip module format. The specific arrangement of PIN diodes in eacharm of a multi-throw switch determines the insertion loss, isolation,incident power handling, sensitivity, linearity, and RF distortion ofeach switch arm. A monolithic (i.e., integrated silicon) solution wouldimprove the overall reliability, circuit ruggedness, performance, size,and overall cost of multi-throw switches as compared to discretesolutions.

Also due to the limitations outlined above, monolithic multi-throwswitches typically incorporate PIN diodes having the same “I” regionthickness for all PIN diodes, regardless of the intended functionalcapability of each switch arm. Presently, monolithic multi-throw HMICswitches use only one “I” region thickness for the PIN diodes in eachswitch arm. This monolithic HIMC approach results in a compromisesolution relative to insertion loss, isolation, power handling,linearity, and distortion, because it does not account for the specificfunctional responses of different switch arms. For example, the primarydesign concerns for a transmit arm in a transmit/receive (T/R) switchinclude incident power handling, isolation, linearity, and distortion,while the receive arm needs to be optimized for insertion loss andsensitivity. These separate RF performance requirements require PINdiodes having different intrinsic “I” region thicknesses.

The concepts described herein achieve fully monolithic solutions forHMIC multi-throw switches using multiple, different “I” regionthicknesses. The solution allows for individual optimization forinsertion loss, isolation, and power handling for each switcharm/termination. The concepts can be relied upon to significantly reducethe size and improve the RF performance of switches as compared tohybrid discrete solutions.

First, a monolithic, vertical, planar semiconductor structure with anumber PIN diodes having different “I” region thicknesses is described.The semiconductor structure includes an N-type silicon substrate, anintrinsic layer formed on the N-type silicon substrate, and a dielectriclayer formed on the intrinsic layer. A number of openings are formed inthe dielectric layer. Multiple anodes are sequentially formed into theintrinsic layer through the openings formed in the dielectric layer. Forexample, a first P-type region is formed through a first one theopenings to a first depth into the intrinsic layer, and a second P-typeregion is formed through a second one of the openings to a second depthinto the intrinsic layer. Additional P-type regions can be formed toother depths in the intrinsic layer. When these PIN diodes of differentintrinsic regions are used in the design of multi-throw switches, theswitches exhibit improved reliability, ruggedness, RF performance, size,and cost as compared to the current discrete solutions.

Additionally, a number of different monolithic, multi-throw PIN diodeswitches are described. The monolithic multi-throw diode switches caninclude a hybrid arrangement of diodes with different intrinsic regions,all formed over the same semiconductor substrate. In one example, twoPIN diodes in a monolithic multi-throw diode switch have differentintrinsic region thicknesses. The first PIN diode has a thinnerintrinsic region, and the second PIN diode has a thicker intrinsicregion. This configuration allows for both the thin intrinsic region PINdiode and the thick intrinsic region PIN diode to be individuallyoptimized. As one example, for a switch functioning in a dedicatedtransmit/receive mode, the first transmit PIN diode can have a thickerintrinsic region than the second receive PIN diode to maximize powerhandling for the transmit arm and maximize receive sensitivity andinsertion loss in the receive arm. FIG. 1A illustrates an examplevertical planar silicon PIN diode structure 100 with multi-thicknessintrinsic regions according to various embodiments described herein. ThePIN diode structure 100, including three PIN diode devices, isillustrated as a representative example in FIG. 1A. Additional PIN diodedevices (i.e., more than three) can be formed as part of the PIN diodestructure 100. The shapes, sizes, and relative sizes of the variouslayers of the PIN diode structure 100 are not necessarily drawn to scalein FIG. 1A. The layers shown in FIG. 1A are not exhaustive, and the PINdiode structure 100 can include other layers and elements not separatelyillustrated. The PIN diode structure 100 can also be formed as part of alarger integrated circuit device in combination with other diodes,capacitors, inductors, resistors, and layers of metal to electricallyinterconnect the circuit elements together to form switches, limiters,and other devices as described below. Additionally, a number of NIPdiode devices can also be formed to have a structure similar to thestructure shown in FIG. 1A, by interchanging the P-type and N-typedopants described below.

The PIN diode structure 100 includes an N-type semiconductor substrate112, an intrinsic layer 114, a first P-type region 116 formed in theintrinsic layer 114, a second P-type region 117 formed in the intrinsiclayer 114, and a third P-type region 118 formed in the intrinsic layer114. The P-type regions 116-118 are formed through openings of widthsW₁-W₃, respectively, in an insulating layer 120 as described in furtherdetail below. The N-type semiconductor substrate 112 forms a cathode ofthe PIN diode structure 100. The P-type regions 116-118 form first,second, and third anodes, respectively, of the PIN diode structure 100.The PIN diode structure 100 also includes a cathode contact 130 formedon the N-type semiconductor substrate 112, a first anode contact 132formed over the first P-type region 116, a second anode contact 134formed over the second P-type region 117, and a third anode contact 136formed over the third P-type region 118.

The PIN diode structure 100 shown in FIG. 1A includes three PIN diodedevices, but the PIN diode structure 100 can be formed to include anysuitable number of PIN diode devices. Electrical contact to the firstPIN diode device is available between the cathode contact 130 and thefirst anode contact 132. Electrical contact to the second PIN diodedevice is available between the cathode contact 130 and the second anodecontact 134. Electrical contact to the third PIN diode device isavailable between the cathode contact 130 and the third anode contact136.

To form the PIN diode structure 100 shown in FIG. 1A, the P-type anoderegions 116-118 can be formed sequentially, or in turn, in the intrinsiclayer 114 as described below with reference to FIG. 1B. The P-type anoderegion 116 is diffused to the least extent into the intrinsic layer 114,the P-type anode region 117 diffused to a greater extent into theintrinsic layer 114, and the P-type anode region 118 is diffused thegreatest extent into the intrinsic layer 114. Thus, the effectiveintrinsic region I₂₁ under the P-type anode region 116 is larger thanthe effective intrinsic region 122 under the P-type anode region 117,and the effective intrinsic region 122 is larger than the effectiveintrinsic region 123 under the P-type anode region 118. In one example,the effective intrinsic region 121 can be between about 20-23 μm, theeffective intrinsic region 122 can be about 12 μm, and the effectiveintrinsic region 123 can be about 5 μm, although other ranges are withinthe scope of the embodiments.

The extent of the lateral diffusions, Ld1, Ld2, and Ld3 of the P-typeregions 116-118 under the insulating layer 120 also vary, with thelateral diffusion Ld1 being the smallest and the lateral diffusion Ld3being the largest. In some cases, to control the capacitance and thehigh-frequency characteristics of each individual PIN diode, the widthsW₁-W₃ of the openings formed in the insulating layer 120 can vary ascompared to each other. For example, W₃ can be smaller than W₂, and W₂can be smaller than W₁.

FIG. 1B illustrates an example method of forming the PIN diode structure100 shown in FIG. 1A. Alternatively, a NIP diode structure can also beformed using the method, by interchanging the P-type and N-type dopants,as described below. Although the method diagram illustrates a specificorder in FIG. 1B, the order or the steps can differ from that which isdepicted. For example, an order of two or more steps can be scrambledrelative to the order shown in some cases. Also, two or more steps shownin succession can be performed, at least in part, at the same time. Insome cases, one or more of the steps can be skipped or omitted. In othercases, additional steps not shown in FIG. 1B can be relied upon, such assteps among or after the steps shown in FIG. 1B.

At step 150, the process includes providing or forming the N-typesemiconductor substrate 112. The semiconductor substrate 112 can beformed by melting and mixing silicon with Arsenic, among other suitabledopants, to a concentration of about 2×10′ Arsenic atoms/cm³ and thensolidifying the mixture, although the substrate 112 can be formed byother methods to other charge carrier concentrations. Additionally oralternatively, step 150 can include providing or sourcing thesemiconductor substrate 112, such as when the semiconductor substrate112 is sourced or purchased from a manufacturer. In another example, aNIP diode structure can be formed using the process shown in FIG. 1B. Inthat case, the process would include forming a P-type semiconductorsubstrate at step 150 using Boron, for example, or another P-type dopantrather than Arsenic.

At step 152, the process includes providing the intrinsic layer 114 overthe semiconductor substrate 112. The intrinsic layer 114 can be providedor formed on the semiconductor substrate 112 using deposition, waferbonding, or another suitable technique. The intrinsic layer 14 can havethe thickness “Th” of between about 7-100 μm as shown in FIG. 1A, insome cases, although the intrinsic layer 14 can be thicker (e.g., up toabout 400 μm) in other cases.

At step 154, the process includes forming the insulating layer 120 overthe intrinsic layer 114. The insulating layer 120 can be formed over theintrinsic layer 114 by wet or dry oxidation in a furnace or reactor,local oxidation over the intrinsic layer 114, or other suitable processstep(s). The insulating layer 120 can be formed as a passivatingdielectric layer of silicon dioxide, among other suitable dielectricinsulators, on the upper surface of the intrinsic layer 14. Theinsulating layer 120 can be formed to a thickness of between about 2000Å and about 5000 Å, although other suitable thicknesses can be reliedupon.

At step 156, the process includes forming a first opening in theinsulating layer 120. Referring back to FIG. 1B, the opening of width W₃can be formed at step 156. The opening of width W₃ can be formed in theinsulating layer 120 by etching a positive photoresist mask using wetchemistry, the application of plasma, or using another suitabletechnique. No other openings are formed at step 156.

At step 158, the process includes implanting the P-type region 118 intothe top of the intrinsic layer 114. The P-type region 118 can be formedby ion implantation or solid source deposition of a high concentrationof P-type dopant through the opening formed in the insulating layer 120at step 156. The P-type region 118 can be formed by doping the intrinsiclayer 114 with Boron, for example, to a concentration of about 2×10¹⁹atoms/cm³, although other P-type dopants can be used to other chargecarrier concentrations to form the junction. When the P-type region 118is formed, a junction is created between the P-type region 118 and theintrinsic layer 114.

Step 158 can also include thermally driving and diffusing the dopingelement for the P-type region 118 into the intrinsic layer 114. A rapid,high temperature, thermal processing or annealing process step can beused for thermal driving. The depth of the P-type region 118 and thesize of the effective intrinsic region 123 can be set by the hightemperature thermal drive. In some cases, the thermal driving at step158 is not relied upon, alone, to diffuse or drive the P-type region 118to the full extent illustrated in FIG. 1A. In some cases, the thermaldriving at steps 162 and 166 can also contribute to the diffusion of theP-type region 118 into the intrinsic layer 114, at least in part, asdescribed below.

Alternatively, to form a NIP diode structure, step 158 can includeimplanting an N-type region into the top of the intrinsic layer 114. TheN-type region can be formed by doping the intrinsic layer 114 withArsenic, for example, or another suitable N-type dopant, to a suitableconcentration. Step 158 can also include thermally driving and diffusingthe N-type dopant into the intrinsic layer 114.

At step 160, the process includes forming a second opening in theinsulating layer 120. Referring back to FIG. 1B, the opening of width W₂can be formed at step 160. The opening of width W₂ can be formed in theinsulating layer 120 by etching a positive photoresist mask using wetchemistry, the application of plasma, or using another suitabletechnique. No other openings are formed at step 160.

In some cases, the width W₂ can be the same as the width W₁. However,one consideration for the PIN diode structure 100 relates to the extentof lateral diffusion, Ld1, Ld2, and Ld3, that results during the hightemperature thermal drives at steps 158, 162, and 166. As the junctiondepths of the P-type regions 116-118 increase, the lateral diffusionsLd1, Ld2, and Ld3 and the overall size of the resulting anodes alsoincrease. In order to control the capacitance and the high-frequencycharacteristics of each individual PIN diode, the physical dimensions ofthe openings formed at steps 156, 160, and 164 can vary as compared toeach other, to control the amount of the lateral diffusion. For example,W₃ can be formed smaller than W₂, and W₂ can be formed smaller than W₁.

At step 162, the process includes implanting the P-type region 117 intothe top of the intrinsic layer 114. The P-type region 117 can be formedby ion implantation or solid source deposition of a high concentrationof P-type dopant through the opening formed in the insulating layer 120at step 160. The P-type region 117 can be formed by doping the intrinsiclayer 114 with Boron, for example, to a concentration of about 2×10¹⁹atoms/cm³, although other P-type dopants can be used to other chargecarrier concentrations to form the junction. When the P-type region 117is formed, a junction is created between the P-type region 117 and theintrinsic layer 114.

Step 162 can also include thermally driving and diffusing the dopingelement for the P-type region 117 into the intrinsic layer 114. A rapidthermal processing or annealing process step can be used for thermaldriving. The depth of the P-type region 117 and the effective intrinsicregion 122 can be set by the high temperature thermal drive. In somecases, the thermal driving at step 162 is not relied upon, alone, todiffuse or drive the P-type region 117 to the extent illustrated in FIG.1A. In some cases, the thermal driving at step 166 can also contributeto the diffusion of the P-type region 117 into the intrinsic layer 114,at least in part, as described below.

Ideally, the thermal driving of the P-type region 117 at step 162 wouldnot impact or change the extent of the diffusion of the P-type region118 into the intrinsic layer 114. However, if this thermal restrictioncannot be met, then the thermal budget for the thermal drive at step 158must incorporate or account for the thermal drive at step 162. In otherwords, the thermal driving at step 162 can also contribute to thediffusion of the P-type region 118 further into the intrinsic layer 114in some cases, and that diffusion can be accounted for when setting thethermal budget for the thermal drive at step 158.

Alternatively, to form a NIP diode structure, step 162 can includeimplanting an N-type region into the top of the intrinsic layer 114. TheN-type region can be formed by doping the intrinsic layer 114 withArsenic, for example, to a suitable concentration, although other N-typedopants can be used. Step 162 can also include thermally driving anddiffusing the N-type dopant into the intrinsic layer 114.

At step 164, the process includes forming a third opening in theinsulating layer 120. Referring back to FIG. 1B, the opening of width W₃can be formed at step 164. The opening of width W₃ can be formed in theinsulating layer 120 by etching a positive photoresist mask using wetchemistry, the application of plasma, or using another suitabletechnique. No other openings are formed at step 164.

At step 166, the process includes implanting the P-type region 116 intothe top of the intrinsic layer 114. The P-type region 116 can be formedby ion implantation or solid source deposition of a high concentrationof P-type dopant through the opening formed in the insulating layer 120at step 164. The P-type region 116 can be formed by doping the intrinsiclayer 114 with Boron, for example, to a concentration of about 2×10¹⁹atoms/cm³, although other P-type dopants can be used to other chargecarrier concentrations to form the junction. When the P-type region 116is formed, a junction is created between the P-type region 116 and theintrinsic layer 114.

Step 166 can also include thermally driving and diffusing the dopingelement for the P-type region 116 into the intrinsic layer 114. A rapidthermal processing or annealing process step can be used for thermaldriving. The depth of the P-type region 116 and the effective intrinsicregion 121 can be set by the high temperature thermal drive. In somecases, the thermal driving at step 166 can also contribute to thediffusion of the P-type regions 117 and 118 into the intrinsic layer114, at least in part. Ideally, the thermal driving of the P-type region116 at step 166 would not impact or change the extent of the diffusionof the P-type regions 117 and 118 into the intrinsic layer 114. However,if this thermal restriction cannot be met, then the thermal budgets forthe thermal drive at steps 158 and 162 must incorporate or account forthe thermal drive at step 166.

Alternatively, to form a NIP diode structure, step 166 can includeimplanting an N-type region into the top of the intrinsic layer 114. TheN-type region can be formed by doping the intrinsic layer 114 withArsenic, for example, to a suitable concentration, although other N-typedopants can be used. Step 166 can also include thermally driving anddiffusing the N-type dopant into the intrinsic layer 114.

The process shown in FIG. 1B can also include process steps to form morewindows and implant additional anodes in the PIN diode structure 10.Additional process steps, including backside processing steps, can alsobe relied upon to form the cathode contact 130 and the anode contacts132, 134, and 136. Other steps can be relied upon to form components onthe PIN diode structure 100, as part of a larger integrated circuitdevice including diodes, capacitors, inductors, resistors, and layers ofmetal to electrically interconnect the components together to formswitches, limiters, and other devices. Particularly, additional stepscan be relied upon to form capacitors, inductors, resistors, and layersof metal to electrically interconnect the components together to formthe monolithic, multi-throw switches described below with reference toFIGS. 6-10 .

FIGS. 1A and 1B encompass monolithic, vertical, planar semiconductorstructures including a number of diodes having different intrinsicregions. The diodes have intrinsic regions of different thicknesses ascompared to each other. The diodes can also be integrated with othercomponents, such as capacitors, resistors, and inductors on themonolithic semiconductor structure in a monolithic circuit format. Themonolithic format can provide a number of advantages over conventionaltechniques where discrete diodes are used, such as smaller size, reducedcost, and better and more controllable frequency response.

The concepts shown in FIGS. 1A and 1B can be extended to other types andarrangements of diode devices. For example, the cathodes of the diodesare electrically connected together in FIG. 1A, although the diodes (andthe cathodes of the diodes) can be separated from each other in otherexample embodiments described below. Additionally, topside contacts canbe formed for both the anodes and the cathodes of the diodes, and thebackside contacts can be isolated for each diode, or even omitted insome cases, as described below. The diodes can also be integrated withother components, such as capacitors, resistors, and inductors on themonolithic semiconductor structure in a monolithic circuit format. Themonolithic format can provide a number of advantages over conventionaltechniques where discrete diodes are used, such as smaller size, reducedcost, and better and more controllable frequency response. According toaspects of the embodiments described below, when these diode devices ofdifferent intrinsic regions are used in the design of a monolithic,multi-throw switch, the switch exhibits improved reliability,ruggedness, RF performance, size, and cost as compared to the currentdiscrete solutions.

Turning to other embodiments, FIG. 2 illustrates an example HMIC siliconPIN diode structure 200 according to various embodiments describedherein. As compared to the diode structure 100 shown in FIG. 1A, thediode structure 200 includes a highly insulative material, such asglass, to form a type of heterolithic microwave integrated circuit(HMIC). The PIN diode structure 200 is illustrated as a representativeexample in FIG. 2 . The shapes and sizes of the layers of the PIN diodestructure 200 are not necessarily drawn to scale. The layers shown inFIG. 2 are not exhaustive, and the PIN diode structure 200 can includeother layers and elements not separately illustrated. Additionally, thePIN diode structure 200 can be formed as part of a larger integratedcircuit device in combination with other diodes, capacitors, inductors,resistors, and layers of metal to electrically interconnect the circuitelements together to form switches, limiters, and other devices. Inother embodiments, one or more NIP diodes can also be formed to have astructure similar to the structure shown in FIG. 2 , by interchangingthe P-type and N-type dopants.

The PIN diode structure 200 includes an N-type semiconductor substrate212, an intrinsic layer 214, and a P-type region 216 formed in theintrinsic layer 214. These layers can be similar in form and size ascompared to the corresponding layers in the structure 100, as shown inFIG. 1A. The N-type semiconductor substrate 212 forms a cathode and theP-type region 216 forms an anode of the PIN diode structure 200. TheP-type region 216 is formed through the opening of width W₂₀ in theinsulating layer 220. The P-type region 216 can be formed to a depth ofbetween about 2-5 μm in the intrinsic layer 214. With a 100 μm thickintrinsic layer 214, for example, the size of the effective intrinsicregion 131 can range between about 8-95 μm.

The PIN diode structure 200 includes a topside anode contact 232 formedover the P-type region 216. The PIN diode structure 200 also includes abackside cathode contact 230 and topside cathode contacts 234A and 234B.Metallic sidewall conductors 240A and 240B extend from and electricallyconnect the backside cathode contact 230 to the topside cathode contacts234A and 234B, and N+-type doped sidewalls 242A and 242B insulate themetallic sidewall conductors 240A and 240B from the intrinsic layer 214.

As shown in FIG. 2 , the N+-type doped sidewalls 242A and 242B and themetallic sidewall conductors 240A and 240B are formed along sidewalls ofthe intrinsic layer 214 and the substrate 212. The sidewalls of theintrinsic layer 214 and the substrate 212 are exposed through verticaletching of the intrinsic layer 214 and the substrate 212, which formsthe intrinsic layer 214 and the substrate 212 into a type of pedestal asshown. The etching process step can be performed, in one example, afterthe P-type region 216 is formed but before the topside anode contact 232and cathode contacts 234A and 234B are formed. Either a wet chemicaletching or a dry etching technique can be relied upon to expose thesidewalls, as deep cavities can be obtained with either technique.

With a substrate 212 of sufficient thickness, the etching process canetch down through the intrinsic layer 214 and into the substrate 212 toa total depth of about 150-160 μm from a topside of the PIN diodestructure 200. If wet chemical etching is relied upon, the sidewalls ofthe intrinsic layer 214 and the substrate 212 can extend down at anangle (e.g., at about 54.7 degrees) from the top surface of the PINdiode structure 200. If dry etching is relied upon, the sidewalls of theintrinsic layer 214 and the substrate 212 can extend substantiallystraight down (e.g., at an angle of about 90 degrees down from the topsurface of the PIN diode structure 200).

The N+-type doped sidewalls 242A and 242B and the metallic sidewallconductors 240A and 240B can be formed after the etching. The N+-typedoped sidewalls 242A and 242B can be formed by diffusing phosphorus, forexample, or another N+-type dopant, into the exposed sidewalls of theintrinsic layer 214 and the substrate 212. The metallic sidewallconductors 240A and 240B can then be formed by depositing metal, such ascobalt silicide (CoSi₂), over the N+-type doped sidewalls 242A and 242B.

The insulator 250 can then be formed around the metallic sidewallconductors 240A and 240B and, if multiple diodes are formed, between thediodes. The application of the insulator 250 can start with a blanketdeposition of about 1500 Å of silicon nitride, for example, by lowpressure chemical vapor deposition (LPCVD), followed by the deposit ofabout 4000 Å of low temperature oxide (LTO). Those layers (although notshown in FIG. 2 ) can encapsulate and protect the diodes during theapplication of the insulator 250. The insulator 250 can then be fusedinto the area around the metallic sidewall conductors 240A and 240B,forming a conformal layer. The insulator 250 can be formed to athickness of at least 50 μm higher than the depth of the vertical etch,to allow for a step of glass planarization.

The insulator 250 can be a borosilicate glass, for example, whichexhibits a low dielectric constant, a low loss tangent, and a thermalcoefficient of expansion similar to silicon for ruggedness over a broadtemperature range, although other types of insulators can be reliedupon. Although a single diode device is illustrated in FIG. 2 , theinsulator 250 can be relied upon to separate a number of different,side-by-side diode devices as described below with reference to FIGS.4A, 4B, and 5 . The insulator 250 also permits a variety of differentelectrical connections among the diodes, by isolating them from eachother.

After the insulator 250 is fused, a number of backside processing stepscan be performed. A backside of the substrate 212 can be ground downuntil the insulator 250 is exposed. The backside cathode contact 230 canthen be formed to extend over the metallic sidewall conductors 240A and240B and the bottom side of the substrate 212. When formed, the backsidecathode contact 230 is electrically connected to the metallic sidewallconductors 240A and 240B. The backside cathode contact 230 is thenelectrically connected to the topside cathode contacts 234A and 234B viathe metallic sidewall conductors 240A and 240B. Thus, with the inclusionof the metallic sidewall conductors 240A and 240B and the topsidecathode contacts 234A and 234B, both anode and cathode contacts areavailable on top of the PIN diode structure 200. As such, the PIN diodestructure 200 is designed to facilitate shunt connections among diodes.

In another embodiment, FIG. 3 illustrates an example HMIC silicon PINdiode structure 300. As compared to the PIN diode structure 300 shown inFIG. 2 , the PIN diode structure 300 also includes an insulatingmaterial layer 260, such as boron nitride or a thermal epoxy, amongother suitable insulators, between the N-type semiconductor substrate212 and the backside cathode contact 230. The semiconductor substrate212 can be etched from the backside of the semiconductor substrate 212to a depth of about 50 μm, opening an area or void for the insulatingmaterial layer 260. Thus, the diode structure 300 is particularlysuitable for series connections among diodes. The cathode contact 230may be optionally included in the embodiment shown in FIG. 3 for thepurpose of mechanical die attachment. In some cases, the cathode contact230 can be omitted.

Both the PIN diode structure 200 shown in FIG. 2 and the PIN structure300 shown in FIG. 3 can be extended to NIP structures. Additionally,both the PIN diode structure 200 and the PIN structure 300 can beextended to include a number of diodes with different “I” regionthicknesses, in a monolithic format, as described below.

FIG. 4A illustrates an example HMIC silicon PIN diode structure 400according to various embodiments described herein. The PIN diodestructure 400 is illustrated as a representative example in FIG. 4A. Theshapes and sizes of the layers of the PIN diode structure 400 are notnecessarily drawn to scale. The layers shown in FIG. 4A are notexhaustive, and the PIN diode structure 400 can include other layers andelements not separately illustrated. Additionally, the PIN diodestructure 400 can be formed as part of a larger integrated circuitdevice in combination with other diodes, capacitors, inductors,resistors, and layers of metal to electrically interconnect the circuitelements together to form switches, limiters, and other devices. Inother embodiments, one or more NIP diodes can also be formed to have astructure similar to the structure shown in FIG. 4A, by interchangingthe P-type and N-type dopants.

The PIN diode structure 400 includes PIN diode devices 360, 362, and364, formed as first, second, and third pedestals. The PIN diode device360 includes an N-type semiconductor substrate 312 and an intrinsiclayer 314, which are formed into a first pedestal by etching asdescribed below. These layers are similar in vertical thickness ascompared to the corresponding layers in the structure 200 shown in FIG.2 . A P-type region 316 is formed in the intrinsic layer 314. The N-typesemiconductor substrate 312 forms a cathode and the P-type region 316forms an anode of the PIN diode device 360. The P-type region 316 isformed through the opening of width W₃₁ in the insulating layer 320. ThePIN diode devices 362 and 364 also include similar N-type semiconductorsubstrate and an intrinsic layers as shown, which are formed into firstand second pedestals, respectively, by etching.

The PIN diode devices 362 and 364 are similar in form and size ascompared to the PIN diode device 360. However, the P-type region 317 isdiffused deeper than the P-type region 316, and the P-type region 318 isdiffused deeper than the P-type region 317. To obtain that form, amethod of manufacturing the PIN diode structure 400 can follow theprocess steps illustrated in FIG. 1B and described above. Particularly,the P-type regions 316-318 can be formed sequentially, or in turn, inthe intrinsic layer 314 according to the process steps shown in FIG. 1B.In that way, the P-type region 316 is diffused to the least extent intothe intrinsic layer 314, the P-type region 317 diffused to a greaterextent into the intrinsic layer 314, and the P-type region 318 isdiffused the greatest extent into the intrinsic layer 314. Thus, theeffective intrinsic region 131 under the P-type region 316 is largerthan the effective intrinsic region 132 under the P-type region 317, andthe effective intrinsic region 132 is larger than the effectiveintrinsic region 133 under the P-type region 318. In one example, theeffective intrinsic region 131 can be between about 20-23 μm, theeffective intrinsic region 132 can be about 12 μm, and the effectiveintrinsic region 133 can be about 5 μm, although other ranges are withinthe scope of the embodiments.

The extent of the lateral diffusions, Ld1, Ld2, and Ld3 of the P-typeregions 316-318 can also vary as described above, with the lateraldiffusion Ld1 being the smallest and the lateral diffusion Ld3 being thelargest. In some cases, to control the capacitance and thehigh-frequency characteristics of the PIN diode devices 360, 362, and364, individually, the widths W₃₁-W₃₃ of the openings formed in theinsulating layer 320 can vary as compared to each other. For example,W₃₃ can be smaller than W₃₂, and W₃₂ can be smaller than W₃₁.

The PIN diode device 360 includes a topside anode contact 332 formedover the P-type region 316. The PIN diode device 360 also includes abackside cathode contact 330 and topside cathode contacts 334A and 334B.Metallic sidewall conductors 340A and 340B extend from and electricallyconnect the backside cathode contact 330 to the topside cathode contacts334A and 334B, and N+-type doped sidewalls 342A and 342B insulate themetallic sidewall conductors 340A and 340B from the intrinsic layer 314.These features can be similar in form and size as compared to thecorresponding features in the structure 200 shown in FIG. 2 . The PINdiode devices 362 and 364 can include similar features as shown in FIG.5A.

The N+-type doped sidewalls 342A and 342B and the metallic sidewallconductors 340A and 340B are formed along sidewalls of the intrinsiclayer 314 and the substrate 312 of the PIN diode device 360. Thesidewalls of the intrinsic layer 314 and the substrate 312 are exposedthrough vertical etching of the intrinsic layer 314 and the substrate312 in a manner similar to that described above with reference to FIG. 2, but among all of the PIN diode devices 360, 362, and 364. Theinsulator 350 can then be formed around the metallic sidewall conductors340A and 340B and the corresponding sidewall features of the PIN diodedevices 362 and 364.

The application of the insulator 350 can start with a blanket depositionof silicon nitride by LPCVD, for example, followed by a deposit of LTO.Those layers (although not shown in FIG. 5A) can encapsulate and protectthe PIN diode devices 360, 362, and 364 during the application of theinsulator 350. The insulator 350 can then be fused into the etched areasaround the PIN diode devices 360, 362, and 364, forming a conformallayer. The insulator 350 can be formed to a thickness of at least 50 μmhigher than the depth of the vertical etch, to allow for a step of glassplanarization. The insulator 350 can be a borosilicate glass, forexample, which exhibits a low dielectric constant, a low loss tangent,and a thermal coefficient of expansion similar to silicon for ruggednessover a broad temperature range, although other types of insulators canbe relied upon.

After the insulator 350 is fused, a number of backside processing stepscan be performed. A backside of the substrate 312 can be ground downuntil the insulator 350 is exposed. The backside cathode contact 330 canthen be formed to extend over the metallic sidewall conductors 340A and340B and the bottom side of the substrate 312. When formed, the backsidecathode contact 330 is electrically connected to the metallic sidewallconductors 340A and 340B. The backside cathode contact 330 is thenelectrically connected to the topside cathode contacts 334A and 334B viathe metallic sidewall conductors 340A and 340B. The PIN diode structure400 is designed to facilitate shunt connections among the PIN diodedevices 360, 362, and 364.

FIG. 4B illustrates another example HMIC silicon PIN diode structure400B according to various embodiments described herein. The PIN diodestructure 400B includes PIN diode devices 360B, 362B, and 364B. The PINdiode structure 400B is similar to the PIN diode structure 400 shown inFIG. 5A. However, as compared to the PIN diode device 360 shown in FIG.4A, the PIN diode device 360B in FIG. 4B also includes the insulatingmaterial layer 352, which is similar to the insulating material layer260 in FIG. 3 . The PIN diode device 362B and 364B also include similarinsulating material layers. Thus, the PIN diode structure 400B is formedfor series connections among the PIN diode devices 360B, 362B, and 364B.The cathode contacts, such as the cathode contact 330, may be optionallyincluded in the embodiment shown in FIG. 4B for the purpose ofmechanical die attachment. In some cases, the cathode contacts can beomitted.

In other examples, a diode structure including a combination of the PINdiode devices 360, 362, and 364, as shown in FIG. 4A, and the PIN diodedevices 360B, 362B, and 364B, as shown in FIG. 4B, can be formedtogether on the same substrate. In that case, a number of PIN diodes canbe arranged in both series and shunt configurations along with variouscomponents in a monolithic circuit format suitable for microwave circuitapplications.

FIG. 5 illustrates an example HMIC silicon PIN diode structure 500according to various embodiments described herein. The PIN diodestructure 500 is illustrated as a representative example in FIG. 5 . Theshapes and sizes of the layers of the PIN diode structure 500 are notnecessarily drawn to scale. The layers shown in FIG. 5 are notexhaustive, and the PIN diode structure 500 can include other layers andelements not separately illustrated. Additionally, the PIN diodestructure 500 can be formed as part of a larger integrated circuitdevice in combination with other diodes, capacitors, inductors,resistors, and layers of metal to electrically interconnect the circuitelements together to form switches, limiters, and other devices. Inother embodiments, one or more NIP diodes can also be formed to have astructure similar to the structure shown in FIG. 5 , by interchangingthe P-type and N-type dopants.

The PIN diode structure 500 includes PIN diode devices 460, 462, and464. The PIN diode device 460 includes an N-type semiconductor substrate412, an intrinsic layer 414, and a P-type region 416 formed in theintrinsic layer 414. The N-type semiconductor substrate 412 forms acathode and the P-type region 416 forms an anode of the PIN diode device460. The P-type region 416 is formed through the opening of width W₄₁ inthe insulating layer 420. The PIN diode device 460 includes a topsideanode contact 432 formed over the P-type region 416. The PIN diodedevice 460 also includes a backside cathode contact 430.

The PIN diode devices 462 and 464 are similar in form and size ascompared to the PIN diode device 460. However, the P-type region 417 isdiffused deeper than the P-type region 416, and the P-type region 418 isdiffused deeper than the P-type region 417. To obtain that form, amethod of manufacturing the PIN diode structure 500 can follow theprocess steps illustrated in FIG. 1B and described above. Particularly,the P-type regions 416-418 can be formed sequentially, or in turn, inthe intrinsic layer 414 according to the process steps shown in FIG. 1B.In that way, the P-type anode region 416 is diffused to the least extentinto the intrinsic layer 414, the P-type region 417 diffused to agreater extent into the intrinsic layer 414, and the P-type region 418is diffused the greatest extent into the intrinsic layer 414. Thus, theeffective intrinsic region I₄₁ under the P-type region 416 is largerthan the effective intrinsic region 142 under the P-type region 417, andthe effective intrinsic region 142 is larger than the effectiveintrinsic region 143 under the P-type region 418. In one example, theeffective intrinsic region 141 can be between about 20-23 μm, theeffective intrinsic region 142 can be about 12 μm, and the effectiveintrinsic region 143 can be about 5 μm, although other ranges are withinthe scope of the embodiments.

Sidewall insulators 415 can also be formed along the sidewalls of theintrinsic layer 414 and the substrate 412 of the PIN diode device 460.The sidewall insulators 415 can include a passivating dielectric oroxide layer. To form the sidewall insulators 415, the sidewalls of theintrinsic layer 414 and the substrate 412 are exposed through verticaletching in a manner similar to that described above with reference toFIG. 2 , but among all of the PIN diode devices 460, 462, and 464. Thesidewall insulators 415 can then be formed on the sidewalls of the PINdiode device 460 and the corresponding sidewalls of the PIN diodedevices 462 and 464, to ensure there are no vertical leakage pathsbetween the anodes and the cathodes in those devices.

The insulator 450 can then be fused among the PIN diode devices 460,462, and 464 in a manner similar to that described above. Theapplication of the insulator 450 can start with a blanket deposition ofsilicon nitride by LPCVD, for example, followed by a deposit of LTO.Those layers (although not shown in FIG. 5 ) can encapsulate and protectthe PIN diode devices 460, 462, and 464 during the application of theinsulator 450. The insulator 450 can then be fused into the etched areasaround the PIN diode devices 460, 462, and 464, forming a conformallayer. The insulator 450 can be formed to a thickness of at least 50 μmhigher than the depth of the vertical etch, to allow for a step of glassplanarization. The insulator 450 can be a borosilicate glass, forexample, which exhibits a low dielectric constant, a low loss tangent,and a thermal coefficient of expansion similar to silicon for ruggednessover a broad temperature range, although other types of insulators canbe relied upon.

After the insulator 450 is fused, a number of backside processing stepscan be performed. A backside of the substrate 412 can be ground downuntil the insulator 450 is exposed. The backside cathode contact 430 canthen be formed to extend over the bottom side of the substrate 412. Insome cases, rather than forming a separate backside cathode contact foreach of the PIN diode devices 460, 462, and 464 as shown in FIG. 5 , asingle backside cathode contact can be formed to extend across theN-type semiconductor substrates of all the PIN diode devices 460, 462,and 464. The PIN diode structure 500 is designed to facilitate shuntconnections among the PIN diode devices 460, 462, and 464.

Because no topside cathode returns are needed for shunt configurationsof PIN diodes, the approach shown in FIG. 5 can be relied upon tocontrol the capacitance of the individual PIN diode devices 460, 462,and 464. In FIG. 5 , the etching process is used to determine thephysical dimensions of the P-type regions 416, 417, and 418, independentof the junction depths of the anodes and the sizes of the windowsW₄₁-W₄₃ in the insulating layer 420. Thus, the concerns regarding theextent of the lateral diffusions, Ld1, Ld2, and Ld3 in the otherembodiments can be controlled according to the approach shown in FIG. 5. In other words, the etching process is used to determine the physicaldimensions of the P-type regions 416, 417, and 418, to control thecapacitance and the high-frequency characteristics of each individualPIN diode.

The diode structures and methods described above can be used tofabricate a wide variety of useful integrated circuits. For example, thediodes described above can be integrated with various components in amonolithic circuit format suitable for microwave circuit applications.The diodes can be integrated with capacitors, resistors, and inductorsformed on the monolithic semiconductor structure. The monolithic formatcan provide a number of advantages over conventional techniques wherediscrete diodes are used, such as smaller size, reduced cost, and betterand more controllable frequency response. According to aspects of theembodiments described below, when diodes of different intrinsic regionsare used in the design of a monolithic multi-throw switch, the switchexhibits improved reliability, ruggedness, RF performance, size, andcost as compared to the current discrete solutions.

FIG. 6 illustrates an example series-connected SPDT switch 700 accordingto various embodiments described herein. The switch 700 is illustratedas a representative example for discussion of the advantages of using amonolithic structure of diodes having different intrinsic regions in thedesign of a monolithic switch. Other arrangements of series-connectedPIN diode switches with additional ports (e.g., series-connected SP3T,SP4T, etc. switches) are within the scope of the embodiments.

As shown in FIG. 6 , the switch 700 includes an RF common port, a firstRF port, a second RF port, a first bias input node, and a second biasinput node. In operation, the switch 700 can either “pass” or “stop” RFsignals between the RF common and the first RF port and the second RFport. Particularly, the switch 700 can either pass or stop an RF signalbetween the RF common and the first RF port based on a voltage biasapplied at the first bias input. The switch 700 can also pass or stop anRF signal between the RF common and the second RF port based on avoltage bias applied at the second bias input.

The switch 700 includes a capacitor 702, a PIN diode 704, and acapacitor 706 electrically coupled or connected in series between the RFcommon and the first RF port. Thus, the PIN diode 704 is electricallycoupled to a node between the RF common and the first RF port. Theswitch 700 also includes a capacitor 708, a PIN diode 710, and acapacitor 712 connected in series between the RF common and the secondRF port. Thus, the PIN diode 710 is electrically coupled to a nodebetween the RF common port and the second RF port. The switch 700includes an RF choke 714 or inductor that is connected at a node betweenthe capacitor 706 and the PIN diode 704 at one and connected to groundat another end. The switch 700 also includes an RF choke 716 or inductorthat is connected at a node between the capacitor 712 and the PIN diode710 at one and connected to ground at another end. The switch 700 alsoincludes a first bias network, including a capacitor 720 connected fromthe first bias input to ground and an RF choke 722 connected from thefirst bias input to an anode of the PIN diode 704. The switch 700 alsoincludes a second bias network, including a capacitor 730 connected fromthe second bias input to ground and an RF choke 734 connected from thesecond bias input to an anode of the PIN diode 710.

In the switch 700, each of the PIN diodes 704 and 710 can be placed intoa “pass” condition when it is forward biased. The PIN diode 704 can beforward biased by application of a sufficient voltage at the first biasinput. The PIN diode 710 can be forward biased by application of asufficient voltage at the second bias input. When forward biased, eachof the PIN diodes 704 and 710 presents a respective low forwardresistance, R_(S), between the RF common and one of the RF ports. Forthe “stop” condition, the PIN diodes 704 and 710 can be zero or reversebiased. When reverse biased, each of the PIN diodes 704 and 710 presentsa high impedance between the RF input and the RF ports.

In series-connected switches, such as the switch 700, insertion loss andpower dissipation are functions of the forward series on-resistance,R_(S), of the PIN diodes 704 and 710. The maximum isolation obtainableis primarily a function of the capacitance, X_(C), of the respective PINdiodes 704 and 710. In a series-connected SPST switch, the insertionloss, IL, and the isolation, ISO, are given (in dB) by:

$\begin{matrix}{{IL} = {20 \cdot {\log_{10}\left\lbrack {1 + \left( \frac{R_{S}}{2 \cdot Z_{0}} \right)} \right\rbrack}}} & (1)\end{matrix}$ $\begin{matrix}{{ISO} = {10 \cdot {\log_{10}\left\lbrack {1 + \left( \frac{X_{C}}{2 \cdot Z_{0}} \right)^{2}} \right\rbrack}}} & (2)\end{matrix}$

For multi-throw series-connected switches, the insertion loss isslightly higher due to mismatch caused by the capacitance of any PINdiodes in “stop” arms. Also, for multi-throw switches, 6 dB can be addedto the isolation figure to account for the 50 percent voltage reductionacross the “stop” arm due to the characteristic impedance of thetermination.

Among other operating characteristics, the forward resistances andcapacitances of the respective PIN diodes 704 and 710 are functions ofthe structural characteristics of the diodes, including the “I” regionthicknesses. Using the techniques and structures described herein, theswitch 700 can be realized monolithically, in a single package, using acombination of one or more PIN diodes with different “I” regionthicknesses. The PIN diodes 704 and 710 can be embodied using acombination of the PIN diodes of the structures shown in FIG. 1A, 4A,4B, or 5, for example, with PIN diodes of different “I” regionthicknesses. For example, if the switch 700 is functioning in adedicated transmit/receive mode, the transmit PIN diode 704 can have athicker “I” region than the receive PIN diode 710 to maximize powerhandling for the transmit arm and maximize receive sensitivity/insertionloss in the receive arm.

While FIG. 6 illustrates an SPDT configuration of the series-connectedswitch 700, the concepts described herein can be extended to have moreports (e.g., up to SP8T or more) and more inputs (e.g., DPDT, etc.). Theconfigurations are also not restricted to one series-connected diode perarm. A SPDT switch can include two, three, or more series-connected PINdiodes in each arm, and each of the series-connected PIN diodes in anygiven arm can have the same or different “I” region thicknesses. Theseconfigurations can also be realized monolithically, in a single package.Using the concepts described herein, a monolithic, multi-throwseries-connected switch with a combination of PIN diodes havingdifferent “I” region thicknesses can be formed.

A process of fabricating the switch 700 can include one or more of thesteps described above with reference to FIG. 1B to form the PIN diodes704 and 710. Additional process steps can be relied upon to form thecapacitors, inductors, transmission lines, bias networks, and otherelements shown in FIG. 6 . The additional circuit elements can be formedover the intrinsic layer of the PIN diodes 704 and 710. Additionalprocess steps can also be relied upon to form the metal layers andrealize the electrical connections between the circuit elements shown inFIG. 6 . For example, the steps can include forming at least one metallayer over the intrinsic layer of the PIN diodes 704 and 710 toelectrically couple the first PIN diode to a node between the common RFport and the first port of the switch 700 and to electrically couple thesecond PIN diode to a node between the RF common port and the secondport of the switch 700.

FIG. 7 illustrates an example shunt-connected SPDT switch 800 accordingto various embodiments described herein. The switch 800 is illustratedas a representative example for discussion of the advantages of using amonolithic structure of diodes having different intrinsic regions in thedesign of a monolithic switch. Other arrangements of shunt-connected PINdiode switches with additional ports are within the scope of theembodiments.

As shown in FIG. 7 , the switch 800 includes an RF common, a first RFport, a second RF port, a first bias input, and a second bias input. Inoperation, the switch 800 can either “pass” or “stop” RF signals betweenthe RF common and the first RF port and the second RF port.Particularly, the switch 800 can either pass or stop an RF signalbetween the RF common and the first RF port based on a voltage biasapplied at the first bias input. The switch 800 can also pass or stop anRF signal between the RF common and the second RF port based on avoltage bias applied at the second bias input.

The switch 800 includes a capacitor 802, a transmission line 804, and acapacitor 806 electrically coupled or connected in series between the RFcommon and the first RF port. The transmission line 804 can be aquarter-wavelength (i.e., λ/4) transmission line in one example, and thecapacitors 802 and 804 can be electrically coupled at any suitableposition along the transmission line 804. The switch 800 also includes acapacitor 808, a transmission line 810, and a capacitor 812 electricallycoupled or connected in series between the RF common and the second RFport. The transmission line 810 can be a quarter-wavelength (i.e., λ/4)transmission line in one example, and the capacitors 808 and 812 can beelectrically coupled at any suitable position along the transmissionline 810.

The switch 800 also includes a PIN diode 814 with an anode connectedbetween the capacitor 806 and the capacitor 802 and a cathode connectedto ground. Thus, the PIN diode 814 is electrically coupled to a nodebetween the RF common port and the first RF port. The switch 800 alsoincludes a PIN diode 816 with an anode connected between the capacitor808 and the capacitor 812 and a cathode connected to ground. Thus, thePIN diode 816 is electrically coupled to a node between the RF commonport and the second RF port. The switch 800 also includes a first biasnetwork, including a capacitor 820 connected from the first bias inputto ground and an RF choke 822 connected from the first bias input to ananode of the PIN diode 814. The switch 800 also includes a second biasnetwork, including a capacitor 830 connected from the second bias inputto ground and an RF choke 834 connected from the second bias input to ananode of the PIN diode 816.

In the switch 800, each of the PIN diodes 814 and 816 can be placed intoa “pass” condition when it is forward biased. For the “stop” condition,the PIN diode 814 can be forward biased by application of a sufficientvoltage at the first bias input. The PIN diode 816 can be forward biasedby application of a sufficient voltage at the second bias input. Whenforward biased, each of the PIN diodes 814 and 816 presents a respectivelow forward resistance, R_(S), to ground. For the “pass” condition, thePIN diodes 814 and 816 can be zero or reverse biased. When reversebiased, each of the PIN diodes 814 and 710 presents a high impedance toground.

Shunt-connected switches offer high isolation for many applications.Because the PIN diodes 814 and 816 can be coupled to a heat sink at oneelectrode, the switch 800 can handle relatively more RF power than theswitch 800 in many cases. In shunt-connected switch designs, such as theswitch 800, isolation and power dissipation are functions of the forwardresistance, R_(S), of the PIN diodes 814 and 816. The insertion loss isprimarily dependent on the capacitance, X_(C), of the respective PINdiodes 814 and 816. In a shunt-connected SPST switch, the insertionloss, IL, and the isolation, ISO, are given (in dB) by:

$\begin{matrix}{{IL} = {10 \cdot {\log_{10}\left\lbrack {1 + \left( \frac{Z_{0}}{2 \cdot X_{C}} \right)^{2}} \right\rbrack}}} & (3)\end{matrix}$${ISO} = {20 \cdot {\log_{10}\left\lbrack {1 + \left( \frac{Z_{0}}{2 \cdot R_{s}} \right)} \right\rbrack}}$$\begin{matrix}{{IL} = {10 \cdot {\log_{10}\left\lbrack {1 + \left( \frac{Z_{0}}{2 \cdot X_{C}} \right)^{2}} \right\rbrack}}} & (4)\end{matrix}$${ISO} = {20 \cdot {\log_{10}\left\lbrack {1 + \left( \frac{Z_{0}}{2 \cdot R_{s}} \right)} \right\rbrack}}$

For multi-throw shunt-connected switches (e.g., the SPDT switch 800shown in FIG. 7 , and greater than double throw), 6 dB can be added tothe isolation figure.

Among other operating characteristics, the forward resistances andcapacitances of each of the PIN diodes 814 and 816 are functions of thestructural characteristics of the PIN diodes 814 and 816, including the“I” region thicknesses. Using the techniques described herein, theswitch 800 can be realized monolithically, in a single package, using acombination of one or more PIN diodes with different structuralcharacteristics and “I” region thicknesses. The PIN diodes 814 and 816can be embodied using a hybrid combination of the PIN diodes shown inFIG. 1A, 4A, 4B, or 5, with PIN diodes of different “I” regionthicknesses. For example, the PIN diode 814 can have a thicker “I”region than the PIN diode 816.

While FIG. 7 illustrates a SPDT configuration of the shunt-connectedswitch 800, the concepts described herein can be extended to have moreports (e.g., up to SP8T or more) and more inputs (e.g., DPDT, etc.). Theconfigurations are also not restricted to one shunt-connected diode perarm. A SPDT switch can include two, three, or more shunt-connected PINdiodes in each arm. Using the concepts described herein, a monolithic,multi-throw shunt-connected switch with any suitable combination of PINdiodes having different “I” region thicknesses can be formed.

A process of fabricating the switch 800 can include one or more of thesteps described above with reference to FIG. 1B to form the PIN diodes814 and 816. Additional process steps can be relied upon to form thecapacitors, inductors, transmission lines, bias networks, and otherelements shown in FIG. 7 . The additional circuit elements can be formedover the intrinsic layer of the PIN diodes 814 and 816. Additionalprocess steps can also be relied upon to form the metal layers andrealize the electrical connections between the circuit elements shown inFIG. 7 . For example, the steps can include forming at least one metallayer over the intrinsic layer of the PIN diodes 814 and 816 toelectrically couple the first PIN diode to a node between the common RFport and the first port of the switch 800 and to electrically couple thesecond PIN diode to a node between the common RF port and the secondport of the switch 800.

FIG. 8 illustrates an example series-shunt-connected SPDT switchaccording to various embodiments described herein. The switch 900 isillustrated as a representative example for discussion of the advantagesof using a monolithic structure of diodes having different intrinsicregions in the design of a monolithic switch. Other arrangements ofseries-connected PIN diode switches with additional ports (e.g.,series-connected SP3T, SP4T, etc. switches) are within the scope of theembodiments.

As shown in FIG. 8 , the switch 900 includes an RF common, a first RFport, a second RF port, a first bias input, and a second bias input. Inoperation, the switch 900 can either “pass” or “stop” RF signals betweenthe RF common and the first RF port and the second RF port.Particularly, the switch 900 can either pass or stop an RF signalbetween the RF common and the first RF port based on a voltage biasapplied at the first bias input. The switch 900 can also pass or stop anRF signal between the RF common and the second RF port based on avoltage bias applied at the second bias input.

The switch 900 includes a capacitor 902, a PIN diode 904, and acapacitor 906 electrically coupled or connected in series between the RFcommon and the first RF port. The switch 900 also includes a capacitor908, a PIN diode 910, and a capacitor 912 connected in series betweenthe RF common and the second RF port. The switch 900 also includes a PINdiode 914 with an anode connected between the PIN diode 904 and thecapacitor 806 and a cathode connected to ground. The switch 900 alsoincludes a PIN diode 916 with an anode connected between the PIN diode910 and the capacitor 912 and a cathode connected to ground. The switch900 also includes a first bias network, including a capacitor 920connected from the first bias input to ground and an RF choke 922connected from the first bias input to a cathode of the PIN diode 904.The switch 900 also includes a second bias network, including acapacitor 930 connected from the second bias input to ground and an RFchoke 934 connected from the second bias input to a cathode of the PINdiode 910.

In the switch 900, the PIN diodes 904 and 914 can be placed into a“pass” condition when forward biased and a “stop” condition when reversebiased based on the voltage at the second bias input. Similarly, the PINdiodes 910 and 916 can be placed into a “pass” condition when forwardbiased and a “stop” condition when reverse biased based on the voltageat the second bias input. When forward biased, each of the PIN diodes904, 914, 910, and 916 presents a respective low forward resistance,R_(S). When reverse biased, each of the each of the PIN diodes 904, 914,910, and 916 presents a high impedance.

It can be difficult to achieve sufficient isolation using a single PINdiode, whether series- or shunt-connected, in an arm of a switch. Toovercome this limitation, there are switch designs that employcombinations of series and shunt diodes (e.g., series-shunt-connected orcompound switches) and switches that employ resonant structures (e.g.,tuned switches) for improved isolation. The series-shunt-connectedconfiguration shown in FIG. 8 is common for this purpose. In theinsertion loss state for a compound switch, the series diode is forwardbiased and the shunt diode is at zero or reverse bias. The reverse istrue for the isolation state. This adds some complexity to the biascircuitry in comparison to simple series- or shunt-connected switches.

In series-shunt-connected switches, such as the switch 900, theinsertion loss, the power dissipation, and the maximum isolation arefunctions of both the forward resistance, R_(S), and the capacitance,X_(C), of the PIN diodes 904, 914, 910, and 916. The power dissipationor loss is mostly limited by and a function of the forward resistancesthrough the series PIN diodes 904 and 910. In a series-shunt-connectedSPST switch, the insertion loss, IL, and the isolation, ISO, are given(in dB) by:

$\begin{matrix}{{IL} = {10 \cdot {\log_{10}\left\lbrack {\left( {1 + \frac{R_{S}}{2 \cdot Z_{0}}} \right)^{2} + \left( \frac{Z_{0} + R_{S}}{2 \cdot X_{C}} \right)^{2}} \right\rbrack}}} & (5)\end{matrix}$ $\begin{matrix}{{ISO} = {10 \cdot {\log_{10}\left\lbrack {\left( {1 + \frac{Z_{0}}{2 \cdot X_{C}}} \right)^{2} + {\left( \frac{X_{C}}{2 \cdot Z_{0}} \right)^{2} \cdot \left( {1 + \frac{Z_{0}}{R_{S}}} \right)^{2}}} \right\rbrack}}} & (6)\end{matrix}$

Among other operating characteristics, the forward resistances andcapacitances of each of the PIN diodes 904, 914, 910, and 916 arefunctions of the structural characteristics of the PIN diodes 904, 914,910, and 916, including the “I” region thicknesses. The switch 900 couldbe implemented with each of the PIN diodes 904, 914, 910, and 916 havingthe same the “I” region thickness. In that case, the arms of the switch900 would be symmetric, and the transmit and receive arms would betreated the same. It would have been necessary in a conventionalmonolithic design for each of the PIN diodes 904, 914, 910, and 916 tohave the same the “I” region thickness. However, a compromise must bemade between the transmit and receive functions in a symmetric switchbecause of the single “I” region thickness. Using the techniquesdescribed herein, the switch 900 can be realized monolithically, in asingle package, using a combination of one or more PIN diodes withdifferent structural characteristics and “I” region thicknesses. The PINdiodes 904, 914, 910, and 916 can be embodied using a hybrid combinationof the PIN diodes shown in FIG. 1A, 4A, 4B, or 5, with PIN diodes ofdifferent “I” region thicknesses. Once a specific arm in the switch 900is chosen for the transmit or receive function, the “I” region thicknessin the respective arm can be optimized for radio frequency performance,by tailoring the “I” region thickness for junction capacitance, anodearea, reverse breakdown, series resistance, any combination of thosecharacteristics, or other electrical characteristics.

As presented in equations (1)-(6), the series on-resistance, R_(S), andthe off-state capacitance, X_(C), leads to basic equations for theinsertion loss IL and isolation ISO of each switch topology, with theassumption that R_(S) and X_(C) of the series and shunt PIN diodes ineach arm are identical. Equations (1)-(5) are first-order approximationsand do not include interconnect parasitics, nor the effect of addingmultiple arms to the switch. In practical designs, these secondaryeffects must be accounted for, and the advantage of quarter wavetransformations in the case of shunt diode designs and impedancematching can be accounted for in all cases.

Examining the effect of the on-resistance characteristic of a typicalactive element, it can be demonstrated by equation (1) that for aseries-only configured switch, the insertion loss IL is dependententirely on the value of the on-resistance and the off-state totaloutput capacitance is essentially decoupled from the switch insertionloss. For a series-shunt configured switch, the output capacitance doesplay a role, but the examination of equation (5) reveals that it is alsodominated by the device on-state series resistance. As another way ofviewing this series resistance dependence for series configuredswitches, the RF energy in the “on” arm is flowing through the activeelement. It can be seen from equations (1)-(5) that the insertion lossand, in direct proportion, the RF power handling is limited by thelosses and dissipation in this series element.

A similar evaluation can be made shunt-only configured switches, asshown in equation (3). In this case the RF energy in the “on” arm is notflowing through the active device, but instead is being transferred frominput to output through low loss, high “Q” transmission lines. In thiscase the RF dissipation is primarily due to I²R losses in the metallicconductors with the active blocking element being DC reverse biased inan off-state. The insertion loss in this shunt configuration, asexpressed in equation (3), is limited only by the output shuntcapacitance. For multi-throw switch configurations, the loss in thequarter wave transformers needs to provide isolation between switcharms, and the IL will result in low values even for active devicestructures that have significant series on-resistance. A difficulty inthis shunt-only switch configuration, as can be seen in equation (4), isthat a high on-state resistance will result in degraded isolation ISO.If the forward on resistance is too high, the isolation in each switcharm may be so poor as to render the switch unusable.

Using these simplified assumptions in equations (1)-(4), it can be seenthat for series-only and shunt-only switch optimizations of the serieson-resistance and the off-state capacitance can dramatically alter highfrequency switch performance. For existing PIN diode monolithic switchdesigns which can only employ a single “I” region thickness, thisoptimization of the individual active elements can only be accomplishedby modifying the active area (anode) of the PIN structure. Theembodiments described herein change that paradigm by allowing eachdiscrete PIN diode to be individually adjusted by allowing the specific“I” region thickness to be modified.

In the series-shunt configuration, it is often found that the highfrequency switch performance is improved by having the series and shuntelements in each arm having differing areas thus modifying the seriesresistance and the off-state capacitance. With existing monolithicdesigns an area change is the only way to affect these changes. Theembodiments described herein, with various PIN diodes havingmulti-thickness “I” regions, provides an additional optimization factorfor monolithic solutions.

While FIG. 8 illustrates a SPDT configuration of the switch 900, theconcepts described herein can be extended to have fewer ports (e.g., aseries-shunt-connected SPST switch) or more ports (e.g., up to SP8T ormore). The concepts can also be extended to have more inputs (e.g.,DPDT, etc.). The configurations are also not restricted to one pair ofseries-shunt-connected diodes per arm. A series-shunt-connected switchcan include two, three, or more series-shunt-connected PIN diodes ineach arm. Using the concepts described herein, a monolithic, multi-throwshunt-connected switch with any suitable combination of PIN diodeshaving different “I” region thicknesses can be formed.

A process of fabricating the switch 900 can include one or more of thesteps described above with reference to FIG. 1B to form the PIN diodes904, 914, 910, and 916. Additional process steps can be relied upon toform the capacitors, inductors, transmission lines, bias networks, andother elements shown in FIG. 8 . The additional circuit elements can beformed over the intrinsic layer of the PIN diodes 904, 914, 910, and916. Additional process steps can also be relied upon to form the metallayers and realize the electrical connections between the circuitelements shown in FIG. 8 .

FIG. 9 illustrates an example series-connected TEE SP3T switch 1000according to various embodiments described herein. The switch 1000 isillustrated as a representative example for discussion of the advantagesof using a monolithic structure of diodes having different intrinsicregions in the design of a monolithic switch. Other arrangements withadditional ports (e.g., series-connected TEE SP4T, etc. switches) arewithin the scope of the embodiments.

As shown in FIG. 9 , the switch 1000 includes an RF common, a first RFport, a second RF port, a third RF port, a first bias input, a secondbias input, and a third bias input. The switch 1000 a first PIN diode1002 in series between the RF common and the first RF port, a second PINdiode 1004 in series between the RF common and the second RF port, and athird PIN diode 1006 in series between the RF common and the third RFport. The switch 1000 also includes bias networks for the first, second,and third, bias inputs as shown in FIG. 9 . In operation, the switch1000 can either “pass” or “stop” RF signals between the RF common andthe RF ports based on voltage biases applied at the first, second, andthird bias inputs.

Among other operating characteristics, the forward resistances andcapacitances of each of the PIN diodes 1002, 1004, and 1006 arefunctions of the structural characteristics of the PIN diodes 1002,1004, and 1006, including the “I” region thicknesses. The switch 1000could be implemented with each of the PIN diodes 1002, 1004, and 1006having the same the “I” region thickness. In that case, the arms of theswitch 1000 would be symmetric, and the transmit and receive arms wouldbe treated the same. It would have been necessary in a conventionalmonolithic design for each of the PIN diodes 1002, 1004, and 1006 tohave the same the “I” region thickness. However, a compromise must bemade between the transmit and receive functions in a symmetric switchbecause of the single “I” region thickness. Using the techniquesdescribed herein, the switch 1000 can be realized monolithically, in asingle package, using a combination of one or more PIN diodes withdifferent structural characteristics and “I” region thicknesses. Once aspecific arm in the switch 1000 is chosen for the transmit or receivefunction, the “I” region thickness in the respective arm can beoptimized for radio frequency performance, by tailoring the “I” regionthickness for junction capacitance, anode area, reverse breakdown,series resistance, any combination of those characteristics, or otherelectrical characteristics.

The PIN diodes 1002, 1004, and 1006 can be embodied using a hybridcombination of the PIN diodes shown in FIG. 1A, 4A, 4B, or 5, with PINdiodes of different “I” region thicknesses. For example, the PIN diode1002 can have a thicker “I” region than the PIN diode 1004, and the PINdiode 1004 can have a thicker “I” region than the PIN diode 1006.

A process of fabricating the switch 1000 can include one or more of thesteps described above with reference to FIG. 1B to form the PIN diodes1002, 1004, and 1006. Additional process steps can be relied upon toform the capacitors, inductors, transmission lines, bias networks, andother elements shown in FIG. 9 . The additional circuit elements can beformed over the intrinsic layer of the PIN diodes 1002, 1004, and 1006.Additional process steps can also be relied upon to form the metallayers and realize the electrical connections between the circuitelements shown in FIG. 9 .

FIG. 10 illustrates an example series-shunt-connected ring switch 1100according to various embodiments described herein. As shown in FIG. 10 ,the switch 1100 includes three RF common ports and three bias inputs. Inoperation, the switch 1100 can either “pass” or “stop” RF signalsbetween the RF common ports based on voltage biases applied at the biasinputs.

In the switch 1100, the node “A” can be electrically coupled to the node“A′,” for a ring switch having three arms. However, the switch 1100 canbe extended to include any number of arms in the ring configuration.Among other components, one arm of the switch 1100 includes aseries-shunt-connection among PIN diodes 1102 and 1104 and aseries-shunt-connection among PIN diodes 1112 and 1114. When forwardbiased, each of the PIN diodes 1102, 1104, 1112, and 1114 presents arespective low forward resistance, R_(S). When reverse biased, each ofthe each of the PIN diodes 1102, 1104, 1112, and 1114 presents a highimpedance.

For series-shunt-connected switches, such as in switch 1100, theinsertion loss, the power dissipation, and the maximum isolation arefunctions of both the forward resistance, R_(S), and the capacitance,X_(C), of the PIN diodes 1102, 1104, 1112, and 1114. The powerdissipation or loss is mostly limited by and a function of the forwardresistances through the series PIN diodes 1102, 1104, 1112, and 1114.Among other operating characteristics, the forward resistances andcapacitances of each of the PIN diodes 1102, 1104, 1112, and 1114 arefunctions of the structural characteristics of the PIN diodes 1102,1104, 1112, and 1114, including the “I” region thicknesses. Using thetechniques described herein, the switch 1100 can be realizedmonolithically, in a single package, using a combination of one or morePIN diodes with different structural characteristics and “I” regionthicknesses. The PIN diodes 1102, 1104, 1112, and 1114 can be embodiedusing a hybrid combination of the PIN diodes shown in FIG. 1A, 4A, 4B,or 5, with PIN diodes of different “I” region thicknesses.

A process of fabricating the switch 1100 can include one or more of thesteps described above with reference to FIG. 1B to form the PIN diodes1102, 1104, 1112, and 1114. Additional process steps can be relied uponto form the capacitors, inductors, transmission lines, bias networks,and other elements shown in FIG. 10 . The additional circuit elementscan be formed over the intrinsic layer of the PIN diodes 1102, 1104,1112, and 1114. Additional process steps can also be relied upon to formthe metal layers and realize the electrical connections between thecircuit elements shown in FIG. 10 .

The switches shown in FIGS. 6-10 are provided as examples, and otherswitch topologies are within the scope of the embodiments. Thestructures and methods described herein can be used to fabricate a widevariety of useful integrated circuits, such as switches, limiters, andother devices. Particularly, combinations of the PIN and NIP diodesdescribed above, with various “I” region thicknesses, can be integratedwith various components (e.g., blocking capacitors, transmission lines,RF chokes, resistors, etc.) in a monolithic circuit format suitable forswitches, limiters, and other devices in microwave circuit applications.

The features of the embodiments described herein are representative and,in alternative embodiments, certain features and elements can be addedor omitted. Additionally, modifications to aspects of the embodimentsdescribed herein can be made by those skilled in the art withoutdeparting from the spirit and scope of the present invention defined inthe following claims, the scope of which are to be accorded the broadestinterpretation so as to encompass modifications and equivalentstructures.

Therefore, the following is claimed:
 1. A method of manufacture of a monolithic multi-throw diode switch, comprising: providing an intrinsic layer on an N-type semiconductor substrate; implanting a first P-type region to a first depth into the intrinsic layer to form a first PIN diode comprising a first effective intrinsic region of a first thickness; implanting a second P-type region to a second depth into the intrinsic layer to form a second PIN diode comprising a second effective intrinsic region of a second thickness; and forming at least one metal layer over the intrinsic layer to electrically couple the first PIN diode to a node between a common port and a first port of the switch and to electrically couple the second PIN diode to a node between the common port and a second port of the switch.
 2. The method of manufacture according to claim 1, wherein the first thickness is greater than the second thickness.
 3. The method of manufacture according to claim 1, further comprising forming at least one capacitor and at least one inductor over the intrinsic layer as part of the monolithic multi-throw diode switch.
 4. The method of manufacture according to claim 1, wherein: the first PIN diode is series-connected in the node between the common port and the first port; and the second PIN diode is series-connected in the node between the common port and the second port.
 5. The method of manufacture according to claim 1, wherein: the first PIN diode is shunt-connected from the node between the common port and the first port to ground; and the second PIN diode is shunt-connected from the node between the common port and the second port to ground.
 6. The method of manufacture according to claim 1, wherein: the first PIN diode is series-connected in the node between the common port and the first port; and the second PIN diode is shunt-connected from a cathode of the first PIN diode to ground.
 7. The method of manufacture according to claim 1, further comprising: forming an insulating layer on the intrinsic layer; forming a first opening in an insulating layer, wherein implanting the first P-type region comprises implanting the first P-type region through the first opening; and after implanting the first P-type region, forming a second opening in the insulating layer, wherein implanting the second P-type region comprises implanting the second P-type region through the second opening, wherein a first width of the first opening is different than a second width of the second opening.
 8. The method of manufacture according to claim 7, further comprising forming a third opening in the insulating layer.
 9. The method of manufacture according to claim 8, wherein a third width of the third opening is different than the second width of the second opening.
 10. The method of manufacture according to claim 8, further comprising implanting a third P-type region through the third opening.
 11. The method of manufacture according to claim 8, further comprising implanting a third P-type region through the third opening to a third depth into the intrinsic layer to form a third PIN diode comprising a third effective intrinsic region of a third thickness.
 12. The method of manufacture according to claim 11, wherein: the first thickness is greater than the second thickness; and the second thickness is greater than the third thickness.
 13. The method of manufacture according to claim 11, wherein: the first depth is greater than the second depth; and the second depth is greater than the third depth.
 14. A method of manufacture of a monolithic multi-throw diode switch, comprising: providing an intrinsic layer on an N-type semiconductor substrate; implanting a first P-type region to a first depth into the intrinsic layer; implanting a second P-type region to a second depth into the intrinsic layer; and forming at least one passive circuit element over the intrinsic layer.
 15. The method of manufacture according to claim 14, wherein the first depth is greater than the second depth.
 16. The method of manufacture according to claim 14, further comprising: forming an insulating layer on the intrinsic layer; forming a first opening in the insulating layer, wherein implanting the first P-type region comprises implanting the first P-type region through the first opening; and forming a second opening in the insulating layer, wherein implanting the second P-type region comprises implanting the second P-type region through the second opening.
 17. The method of manufacture according to claim 16, wherein a first width of the first opening is different than a second width of the second opening.
 18. The method of manufacture according to claim 16, further comprising forming a third opening in the insulating layer.
 19. The method of manufacture according to claim 18, further comprising implanting a third P-type region through the third opening to a third depth into the intrinsic layer.
 20. The method of manufacture according to claim 19, wherein: the first depth is greater than the second depth; and the second depth is greater than the third depth. 